TYPE |
8 ANALOG INPUTS 16 BITS SPGA ; FILTER & ADC per CHANNELS
|
| INPUTS |
|
| - Number of channels |
8 differential inputs |
| - Levels |
± 10V FS G = 1 |
| - Peak voltage |
± 40V without any loss |
| - Input impedance |
ZIN ≥ 2M Ω + R matching possible |
| - Solftware-program. gains per channel |
1 ; 2 ; 4 ; 8 |
| - Gain accuracy |
≥ ± 0.005% G = 1 |
| - Common mode rejection |
≥ ± 0.02% G = Gmax |
104 dB G = Gmax |
| - Settling time at 0.01% |
3µs ∆V = 20V |
| - Inter-channel modulation |
≤ 120 dB |
- Gain and offset drift
|
± 5 ppm/°C 1µV/°C
|
| FILTERS |
|
| - Selection |
With or without filter by software |
| - Type |
8th order (BU)or (BE) |
| - Process |
Switched capacities |
| - Cut-off frequency |
Programmable from 10Hz to 40KHz (- 3dB) |
| - Bandwidth ripple |
≤ ± 0.15dB of DC at 0.7 CF (CF max = 40KHz, F. ext.) |
| - Transition slope |
78dB / octave |
| - Attenuation at 2 CF |
≥ 72dB |
| - Signal to noise |
≥ 76dB from 2 CF to 200KHz |
| - Phase gap between channels |
≤ ± 0.5° from DC to 0.8 CF (± 1° max.) |
| - Cut-Off Frequencies |
Spectral band ≤ 98 Fc |
- Groups
|
Cut-off frequency selection in groups of 2 channels (V0/V1; V2/V3; V4/V5; V6/V7) 1 on FRONT panel
|
| - External frequency |
TTL TRIGGER level cyclic ratio 1/2 (Fc max. = 2 MHz) |
|
FClock = 50 x max. Fcut-off desired |
| - Internal frequency |
2MHz |
| - CF Av/group with FClock = 8MHz |
15 ratios available for each group
10 ; 20 ; 40 ; 80 ; 100 ; 200 ; 400 ; 800Hz
1 ; 2 ; 4 ; 8 ; 10 ; 20 ; 40KHz |
| S/H + ADC |
|
| - Converter |
S/H-integrated type 16 bits |
| - Conversion time |
3µs / 200KHz max. |
| - Encoding |
Binary offset without any code missing |
| - Integral and differential non-linearity |
± 1 LSB typical |
| - Signal-noise ratio |
≥ 86 dB |
| - Quantifying noise |
≤ 0.8 LSB max. |
| - Distorsion |
- 94 dB (45 KHz) |
| - Gain and offset stability |
± 5ppm/°C and ± 3ppm/°C |
| - S/H time |
40ns max. |
- Reference
|
2.5V ; 5ppm/°C
|
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French Version
